See also Can num++ be atomic for 'int num'? re: x86 atomic RMWs generally speaking, a considerably less concise clarification of the identical factor you wrote below.
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Atomic guarantees that usage of the property are going to be done in an atomic manner. E.g. it normally return a totally initialised objects, any get/set of a home on one thread need to finish just before One more can obtain it.
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To accessibility that cache line one other core has to get access legal rights initial, as well as protocol to get those legal rights entails the current operator. In impact, the cache coherency protocol helps prevent other cores from accessing the cache line silently.
Mackie MesserMackie Messer 7,32833 gold badges3737 silver badges4141 bronze badges 1 Basically, cache-line-break up locked instructions are disastrously sluggish (much like the outdated bus-lock system that stalls memory obtain by all cores), so gradual that there is a perf counter function especially for that, and up to date CPUs have additional assistance for creating that always fault to enable detection of stray use even in VMs, and so on.
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Sadly, "atomic = non-relation" isn't what you're going to listen to. (However Codd was not the clearest author and his expository remarks get baffled together with his base line.
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Yet another difference is the fact atomic Homes will keep/release cycle your objects in the getter.
a thread contacting m2 could examine 0, 1234567890L, or Various other random value because the assertion i = 1234567890L will not be certain to be atomic for an extended (a JVM could write the 1st 32 bits and the last 32 bits in two operations and a thread could observe i between).
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It really is like having a retina Exhibit and One more Show at Atomic Wallet fifty periods the resolution. Why waste the assets for getting that degree of performance if it helps make no change to any person? Particularly when strong code can save days of debugging...
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